1. Field of Invention
This invention relates generally to memory arrays and specifically to sense amplifiers of a DRAM array.
2. Description of Related Art
Dynamic RAM (DRAM) constitutes the main memory of most personal computers and accounts for nearly 70% of the global semiconductor memory market. Since DRAM is less expensive and much slower than Static RAM (SRAM), system optimization requires a precise balance between DRAM's cost savings and DRAM's slower speeds. For example, while typical microprocessor speeds exceed 300 Mhz, DRAM speed is typically less than 100 Mhz. Thus, system optimization may be increased by increasing DRAM speed.
Further, DRAMs involve a tradeoff between supply voltage and speed. While higher supply voltages result in faster charging times, and thus greater DRAM speeds, fast charging times at high supply voltages result not only in increased power consumption but also in supply voltage fluctuations. These fluctuations in the supply voltage, in turn, may result in read speed fluctuation and even erroneous data interpretation. It is therefore desirable to compensate for these supply voltage fluctuations.
For example, a conventional DRAM 10 is shown in FIG. 1 as including a DRAM cell array 20 having a plurality of DRAM cells arranged in n+1 columns by m+1 rows. The cells in the DRAM array 20 are well known and are thus not shown in FIG. 1 for simplicity. The cells in a common row are coupled to an associated word line WL, and the cells in a common column are coupled to associated complementary bit lines BL and BL. A plurality of sense circuits 30 are coupled between respective pairs of the complementary bit lines BL and BL and a sense logic circuit 40. A PMOS bias transistor MP1 selectively couples the sense circuits 30 to V.sub.cc in response to an enable signal Pbias, and an NMOS bias transistor MN1 selectively couples the sense circuits 30 to ground potential in response to an enable signal Nbias.
Referring to FIG. 2, the sense circuits 30 include a cross coupled latch formed by two CMOS inverters connected between the bias transistors MN1 and MP1. The input terminal of the first CMOS inverter, which is formed by an NMOS transistor MN2 and a PMOS transistor MP2, is coupled to the output terminal of the second CMOS inverter, which is formed by an NMOS transistor MN3 and a PMOS transistor MP3, and to the bit line BL, i.e., node N1. The input terminal of the second CMOS inverter is coupled to the output terminal of the first CMOS inverter and to the complementary bit line BL, i.e., node N2.
The cells within the array 20 represent binary information by the presence or absence of charge therein. Thus, for instance, a cell within the array 20 represents a binary "1" when there is charge stored therein and, conversely, represents a binary "0" when there is no charge stored therein. Cells are selected for read operations in a well known manner using row address strobe (RAS) and column address strobe (CAS) signals. Specifically, the row address of a cell desired to be read is clocked into the DRAM 10 on the falling edge of the RAS signal. In response thereto, suitable row decoders (not shown) enable the word line WL corresponding to the received row address. Column addresses are clocked into the DRAM 10 on the falling edge of the CAS signal, thereby facilitating the latching of binary cell data from the selected row of cells into the sense circuits 30.
The sense circuits 30 are enabled on the falling edge of the RAS signal by driving signal Pbias to logic low, e.g., ground potential, and driving signal Nbias to logic high, e.g., V.sub.cc. The low Pbias signal turns on PMOS bias transistor MP1 and thereby couples the sources of PMOS transistors MP2 and MP3 to V.sub.cc, while the high Nbias signal turns on the NMOS bias transistor MN1 and thereby couples the sources of NMOS transistors MN2 and MN3 to ground potential. In order to avoid creating a short circuit between V.sub.cc and ground potential, signals Pbias and Nbias are not simultaneously enabled.
During read operations, a differential voltage develops across the complementary bit lines BL and BL associated with cells in the selected row. The polarity of this differential voltage depends upon the binary state of the cell, i.e., upon the presence or absence of charge therein. For instance, if a cell is charged, thereby representing a binary "1", its bit line BL is at a first voltage and its complementary bit line BL is at a second voltage, where the first voltage is greater than the threshold voltage of the CMOS inverters within the sense circuits 30 (V.sub.T), and the second voltage is less than V.sub.T. Conversely, if a cell is uncharged, thereby representing a binary "0", its bit line BL is at the second voltage and its complementary bit line BL is at the first voltage.
Once the sense circuits 30 are enabled, the differential voltage across the complementary bit line pairs BL and BL drives the cross-coupled latch within the associated sense circuit 30 to a corresponding binary state. For instance, if the selected cell is charged, i.e., representing a "1", the first voltage on the bit line BL turns on NMOS transistor MN2 and turns off PMOS transistor MP2, thereby driving node N2, and thus the complementary bit line BL, low to ground potential. The low potential at node N2, in turn, turns on PMOS transistor MP3 and turns off NMOS transistor MN3, thereby driving node N1, and thus the bit line BL, high to V.sub.cc. Conversely, if the selected cell is uncharged, the sense circuit 30 associated therewith drives the corresponding complementary bit lines BL and BL to ground potential and V.sub.cc, respectively.
The differential voltages developed across the complementary bit lines BL and BL via the sense circuits 30 are decoded and then sensed in a well known manner in the logic sense circuit 40 which, in turn, provides an output signal OUT indicative of the binary state of the selected DRAM cell.
As mentioned above, the sense circuits 30 are simultaneously enabled by turning on the PMOS bias transistor MP1 and then the NMOS bias transistor MN1. Since typical DRAM arrays typically include 1024 or more columns, simultaneously enabling 1024 or more of the sense circuits 30 sources large currents from the supply voltage V.sub.cc. These large currents sourced from V.sub.cc result not only in undesirable power consumption but also in unwanted noise. If sufficiently large, voltage supply noise may invalidate data and even damage associated logic.
Further, the current sourced to the sense circuits 30 may pull down the supply voltage V.sub.cc by as much as 20%. For instance, where V.sub.cc is a 3.0 volt supply, the simultaneous enabling of the sense circuits 30 may pull V.sub.cc down to 2.3 volts. Such fluctuations in V.sub.cc result in several problems, including data corruption, ground bounce, logic damage, junction breakdown, and so on.
In order to minimize supply voltage fluctuations resulting from enabling the sense circuits 30, additional PMOS bias transistors MP1(x) may be coupled between V.sub.cc and the sense circuits 30 and additional NMOS bias transistors MN1(x) may be coupled between ground potential and the sense circuits 30, as shown, for instance, in FIG. 3. Here, the bias transistors MP1(x) and MN1(x) are smaller in size, and thus current carrying capacity, than the respective bias transistors MP1 and MN1 shown in FIGS. 1 and 2. Further, buffer delays 32 are added in the Pbias and Nbias signal paths, as shown in FIG. 3, such that the bias transistors MP1(x) and MN1(x) are turned on in a sequential manner by respective signals Pbias and Nbias. In this manner, current sourced from V.sub.cc to the sense circuits 30 is gradually increased to a maximum value. As a result, power consumption and supply voltage noise resulting from current flow to the sense circuits 30 of FIG. 3 is reduced, as compared to that of FIG. 1.
However, replacing bias transistors MP1 and MN1 (FIG. 1) with numerous smaller respective bias transistors MP1(x) and MN1(x) (FIG. 3) undesirably degrades DRAM read speeds at low V.sub.cc. For instance, where V.sub.cc is 2.7 volts, each of the bias transistors MP1(x) of FIG. 3 charges the cross-coupled latches within the sense circuits 30 to only 2.7 volts, as compared to 4 volts when a 4 volt V.sub.cc is utilized. As a result, gradually increasing current sourced from V.sub.cc to sense circuits 30 at low V.sub.cc in the manner described above with respect to FIG. 3 requires longer charge times. Thus, although advantageously reducing power consumption and noise at high V.sub.cc, introducing delays into the Pbias and Nbias signal paths as illustrated in FIG. 3 will, at low V.sub.cc, undesirably limit DRAM read speed.